The purpose of this lab exercises is to help you become familiar with simple serial communication protocols by
working the UART protocol which is both one of the most widely used simple serial protocols and contains a lot of
the core aspects used in more advanced communication protocols.
It is important to note, that given the fundamentally parallel and interactive nature of hardware designs, debugging
designs described with HDL code requires a method that strictly identifies and leverages guaranteed cause-effect
relationships with in the design’s description. Other lazy or speculative debugging methods will generally result in
vast amounts of wasted time, effort, and frustration and can easily increase debugging times by a factor of 10x.
In this lab, you will perform the following tasks:
• Design and test via a test bench the timer unit for the Receiver Block of the UART
• Design and test via a test bench the receiver control unit (RCU) for the UART Receiver Block
• Combine the RCU block, timer block, and the given blocks in order to create the UART Receiver Block
• Develop a test bench from a given template to test the functionality of the UART Receiver Block created
• Synthesize the UART Receiver Block using Design Compiler®
• Test the Synthesized/Mapped version of the UART Receiver Block
• Submit electronically your completed UART receiver block to be graded
In a UNIX terminal window, issue the following commands, to setup your Lab 6 workspace:
mkdir –p ~/ece337/Lab6
The setup6 command is an alias to a script file that will check your Lab 6 directory structure and give you file
needed for starting the lab. If you have trouble with this step please ask for assistance from your TA.
IMPORTANT: Make sure to add this new workspace into your 337 Repository, like you did in Lab1.
This way, you will always have the original copy in storage.
To prepare for implementing your UART design you must complete the following:
• Create a complete state transition diagram for the Receiver Control Unit (RCU) described in Section 5.3
• Create a complete waveform diagram for the timer unit described in Section 5.2 via utilizing
www.wavedrom.com and the provided ’timer.json’ template code.
• Create a complete RTL diagram for the RCU block described in Section 5.3
• Create a block diagram showing how you are going to build your timer unit using the flex_counter module
from Lab 4
You must have these diagrams submitted as either PDF file(s) or image files using common standards (JPEG,
PNG, or BMP) via “submit Lab6prep” in order to earn points for them. Lab6prep is due 2:30AM the day
before the autograder submission deadline. (i.e) For Tuesday Lab students, the autograder submission is due
2:30AM the next Tuesday and Lab6prep is due 2:30AM on Monday
It is highly recommended that you complete all of these diagrams prior to starting to write any design code, as this
should save you tremendous amounts of time debugging/rewriting code later on.
NOTE: All diagrams, both RTL and state transition diagrams, must be done as a digital drawing. Hand drawn
diagrams (even if they are scanned) will receive a grade of zero points. There are multiple easy ways to make
digital diagrams available to you in the labs and through free software. Four recommendations are (1) Microsoft’s
Visio (available in Windows labs on campus), (2) the free ware program called DIA (available for both Linux
and windows machines), (3) Libre Draw (available on the Linux machines), and (4) https://www.draw.io/
(highly recommended alternative to Visio).
In Lab 6 you will be working on part of the design of a Universal Asynchronous Receiver Transmitter (UART).
From the first day of class, you have been gathering the knowledge and expertise with the tools to allow you to
complete this design. At this point in the course, you should know, and will be expected to know, how to operate
all the tools that were introduced to you in the prior labs. This lab is structured to mimic what you would encounter
should you choose to pursue a career as an ASIC/VLSI designer upon graduation. Essentially you, the designer,
are being provided with a set of specifications for a design, including the protocol that it is supposed to support, the
functionality it is supposed to perform, and an architecture for how to modularize the needed internals of the design.
In general, as you gain experience design ASICs and systems you will be expected to play increasing larger roles in
developing the architecture for a design instead of just implementing a provided architecture. In industry, you will
most likely be working together with other people in designing your ASIC. Therefore, some blocks in your design
will be written by other people and you will be required to understand how they work in order to be able to interface
them to create a working design. In this lab, you have been given complete modules for most of the blocks other
than the top-level block, which are described in Section 6. You also have been given a test bench template. You will
need to design and test the blocks described in Section 5, which includes the top-level block. You are not and will
not being specifically instructed on how to design these blocks, only their intended behavior/function. You are only
told the expected architecture for the design, which is comprised of the inputs to each block, the outputs from each
block and what function the block is to perform. It is up to you to come up with a working solution for your blocks
and then integrate the 8 building blocks to form the Receiver block.